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16–4
Table 16–4. Complex AddSub Block Inputs and Outputs
Chapter 16: Complex Type Library
aclr
R
Signal
Direction
Input
Output
Description
Optional asynchronous clear.
Result.
Table 16–5 shows the Complex AddSub block parameters.
Table 16–5. Complex AddSub Block Parameters
Name
Number of Inputs
Add (+) Sub (–)
Enable Pipeline
Clock Phase Selection
Use Enable Port
Use Asynchronous Clear Port
DSP Builder Handbook
Value
>= 2
User defined
On or Off
User Defined
On or Off
On or Off
Description
Specifies the number of input wires to combine.
Specify addition or subtraction operation for each port with the characters +
and –. For example + – + implements +a – b + c for three ports.
DSP Builder implements the block as a tree of 2-input adders. Each
consecutive pair of inputs are + +, + – or – +. However, none of the input
adders can have two consecutive subtractions. Thus, + – – + is valid (as the
two input adders are parameterized + – and – +), + – – + + is also valid but
+ + – – + is not valid.
Missing operators are assumed to be +.
When this option is on, DSP Builder registers the output from each stage in
the adder tree, resulting in a pipeline length that is equal to
ceil(log2(number of inputs)) .
When you enable pipeline, you can specify the phase selection as a binary
string, where a 1 indicates the phase in which the block is enabled. For
example:
1 —The block is always enabled and captures all data passing through
the block (sampled at the rate 1).
10 —The block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100 —The block is enabled on the second phase of and only the second
data of (sampled at the rate 1) passes through. That is, the data on
phases 1, 3, and 4 do not pass through the block.
Turn on to use the clock enable input ( ena ).
Turn on to use the asynchronous clear input ( aclr ).
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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